This invention is in the field of electronic systems, and is more specifically directed to synchronous operation of such systems.
As is fundamental in the art, many modern electronic systems include numerous electronic functions that operate in conjunction with one another. These functions may be embodied in multiple integrated circuits that communicate with one another, or may be integrated into a single large-scale integrated circuit in a form commonly referred to in the art as a “System-on-Chip” (SoC). In such systems, activity within each integrated circuit or electronic function is often coordinated by clock signals that are generated on-chip. In larger-scale electronic systems, each function typically has its own clock frequency requirement, yet the multiple functions in the overall system communicate with one another in a synchronous or clocked manner. For example, consumer-oriented systems such as televisions and home theaters include video decoders for decoding an input video signal into digital video output signals that are synchronized with a synchronization pulse contained within the incoming video signal itself. Modern spread-spectrum communications transmitters and receivers require the generation of high-frequency clock signals for the modulation and demodulation, respectively, of signals over the multiple subchannels of the spread spectrum bandwidth. In these and other electronic systems, the generation of periodic signals for clocking the operation of circuit functions based upon a system clock or synchronization pulse, is a common and often critical function.
A conventional approach for generating periodic signals based upon a reference clock utilizes the well-known phase-locked loop (“PLL”). In general, PLL circuits operate by comparing the time at which an edge of a reference clock is received with a corresponding edge of an internally generated clock, and generating an error signal that is used to adjust the generated clock signal to better match the received reference clock. The goal of these conventional PLLs, whether implemented in analog or digital form, is to generate a periodic clock signal of the desired frequency.
In recent years, significant advances in the field of clock generation include clock generator circuits that generate a clock signal at the desired frequency but considered as an average over time. In other words, each period of the generated clock signal is not necessarily the same as others, but rather the generated clock periods average out over time to the desired frequency. Many digital systems can use time-average-frequency-based clock signals with little or no deleterious effect on system performance. By removing the constraint that each cycle of the generated clock signal must have the same period, the clock generation circuitry can be implemented in a much more efficient and robust manner, and largely in the digital domain.
Examples of clock generator circuits that incorporate a “flying-adder” architecture operating according to the time-average-frequency concept, and system applications of such circuits, are described in Mair and Xiu, “An Architecture of High-Performance Frequency and Phase Synthesis”, J. Solid State Circ., Vo. 35, No. 16 (IEEE, June, 2000), pp. 835-46; commonly assigned U.S. Pat. No. 6,329,850 B1; commonly assigned U.S. Pat. No. 6,940,937 B2; commonly assigned U.S. Pat. No. 7,065,172 B2; commonly assigned U.S. Pat. No. 7,356,107 B2; commonly assigned U.S. Pat. No. 7,372,340 B2; U.S. Patent Application Publication No. US 2007/0055718 A1; and U.S. Patent Application Publication No. US 2008/0021944 A1; all such documents incorporated herein by this reference.
A rigorous mathematical treatment of the concept of time-average-frequency clock generation, and more specifically of the flying-adder architecture for synthesizing signals according to that concept, is provided in Xiu, “The Concept of Time-Average-Frequency and Mathematical Analysis of Flying-Adder Frequency Synthesis Architecture”, IEEE Circuits and Systems Magazine, Vol. 8, No. 3 (Third Quarter 2008), pp. 27-51, incorporated herein by reference.
FIG. 1 illustrates a simple example of a clock generator circuit (frequency synthesizer) constructed according to the “flying-adder” architecture. In this example, a conventional phase-locked loop shown as PLL 4 generates multiple evenly-spaced (by duration Δ) VCO phases VCO_PH, at a frequency that is locked to a reference frequency generated by frequency reference 2. Frequency reference 2 may be implemented as a crystal oscillator or other reference external to PLL 4. Frequency synthesizer 10 includes multiplexer 6, which has multiple inputs, each receiving one of the multiple output phases VCO_PH generated by a voltage controlled oscillator (VCO) within PLL 4. Multiplexer 6 selects one of VCO phases VCO_PH for coupling to its output in response to a digital value received at its select input. This select value is generated by accumulator 8 within frequency synthesizer 10, more specifically from the integer portion of the contents of accumulator 8. Accumulator 8 sums the value of digital frequency control word FREQ with its current contents (integer and fractional), and stores that sum in its integer and fractional portions. The integer portion of the contents of accumulator 8 constitutes the select input of multiplexer 6, and thus indicates the desired VCO phase to be applied to the clock input of D-type flip-flop 9, which is configured to generate alternating levels at its output on line CLKOUT in response to each received clock edge.
In this arrangement, the pulse width of each half-cycle of clock CLKOUT amounts to the delay Δ between adjacent phases VCO_PH times the incremental difference in successive integer values output by accumulator 8. As described in the above-incorporated articles, patents, and patent publications, some desired frequencies for the generated time-average-frequency clock signal require a digital control word value that necessarily includes a non-zero fractional portion. As a result, the accumulator in the flying-adder architecture will periodically generate a carry-in from its fractional portion to its integer portion. As the fractional portion of the contents of accumulator 8 rolls over to generate a carry into the integer portion, the incremental difference in successive integer values output by accumulator 8 (and thus the duration between edges of the phase selected by multiplexer 6) increases from that of the previous cycle. The resulting output clock signal in the cycle (or half-cycle) corresponding to that carry-in event will necessarily be prolonged from the previous cycle, typically by the duration of one delay Δ between adjacent phases VCO_PH.
FIG. 2 illustrates an example of a system application of frequency synthesizer 10, in the context of a receiver for MPEG2 data streams, for example as may be included within a television set or a set-top box for a television set. In this example, as described in Xiu, “A Novel DCXO Module for Clock Synchronization in MPEG2 Transport System”, IEEE Trans. on Circuits and Systems, Vol. 55, No. 8 (September 2008), pp. 2226-37, incorporated herein by reference, input data stream DATA/PCR includes the video and audio payload, along with a program clock reference (PCR) serving as a timestamp, and useful for recovering a synchronous clock signal from the data stream. In this system, time stamp processor 12 receives the PCR and generates digital control word FREQ, which is applied to flying-adder synthesizer 10. Flying-adder synthesizer 10 operates as a frequency synthesizer in the manner described above relative to FIG. 1, selecting among the clock phases generated by PLL 4 based on the frequency reference of crystal oscillator 2, as described above. Flying-adder synthesizer 10 generates a clock signal CLKOUT that is applied to RF modulator 14 and DAC 15. Clock signal CLKOUT is intended to have a frequency corresponding to that of the payload data in data stream DATA/PCR, so that processing by RF modulator 14 and DAC 15 is synchronous with that data stream. Nominally, the frequency of clock signal CLKOUT should correspond to the reference frequency from crystal oscillator 2, although the actual clock signal CLKOUT will be generated synchronously with the clock recovered from the PCR.
While the time-averaged frequency of output CLKOUT corresponds to the desired clock frequency (the clock recovered from the input datastream) in this situation, as described above, instantaneous changes in the clock period occur for at least one cycle as the fractional portion of the digital control word FREQ is accumulated and generates carry into the integer portion of the accumulator. More specifically, as described in the Xiu article, consider a frequency control word value FREQ=I+r, where I constitutes the integer portion and r constitutes a non-zero positive-valued fractional portion. The time-average period Tavg of the output clock signal will thus be:Tavg=(I+r)*ΔIn this case, the output clock signal would have some cycles of a duration I*Δ, and some cycles of a duration (I+1)*Δ, and the rate at which the cycles of duration (I+1)*Δ occur is |r|. For example, if r=0.01, then one cycle of duration (I+1)*Δ will occur in every 100 cycles of the signal on line CLKOUT. Similarly, if r=0.90, then one cycle of duration I*Δ and nine cycles of duration (I+1)*Δ will occur in every ten cycles of the signal CLKOUT. In many system applications, this modulation in instantaneous clock periods has little noticeable effect.
However, it has been observed that this phase modulation can have an undesired impact in applications in which clock signal CLKOUT is used to drive such circuitry as digital-to-analog converters (DACs) and analog-to-digital converters (ADCs), such as in the case of the system of FIG. 2 in which clock signal CLKOUT is clocking the operation of DAC 15. In short, DACs, ADCs, and some other downstream processing circuitry operate on the assumption that the sample times are evenly-spaced, and thus on the assumption that the sample clock has evenly-spaced edges. Deviation from that evenly-spaced condition necessarily causes distortion in the sampled signal, particularly at the high signal frequencies present in the RF output of the MPEG2 video receiver example of FIG. 2.
FIG. 3 illustrates an example of the frequency spectrum of output clock CLKOUT from a conventional flying-adder frequency synthesizer such as that of FIG. 1 in the system of FIG. 2, as measured from the output of DAC 15. In this example, the desired time-averaged signal frequency is 66.75 MHz, which appears as peak 16 in the spectrum of FIG. 3. The offset value corresponding to fractional portion r in this example is −150 ppm. As a result, because of the lengthened cycles that are periodically inserted into the clock signal train, spurious peaks 18 appear on each side of the fundamental output frequency, as shown in FIG. 3. These peaks will be reflected in distortion in the output signal RF_OUT based on the received input datastream, and thus distortion in the displayed audio and video information.
It has been observed, in connection with this invention, that these spurious components in the spectrum of the sampling clock, for example as applied to a high-speed DAC, can result in distortion of high bandwidth data being processed, especially as r becomes large. For example, in those systems such as processing of high frequency composite audio and video signals in an RF modulator, the digital control word (i.e., FREQ) is based on the frequency of a clock that is recovered from the incoming data stream itself. As such, even if the flying-adder synthesizer is designed to minimize phase modulation in its generated clock signal, offset relative to the nominal frequency will still generally be present in the actual signal (i.e., r≠0), resulting in undesirable distortion in the processed signal.
As described in the Xiu article incorporated by reference above, randomization techniques such as dithering have been used to reduce the amplitude of the spurious jitter components (e.g., peaks 18 of FIG. 3). While such randomization in fact reduces those peaks, the noise level of the system and the downstream processing such as sampling is necessarily increased as a result.